Browse Prior Art Database

Sequence Checking of Storage Control Line

IP.com Disclosure Number: IPCOM000084098D
Original Publication Date: 1975-Sep-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Manyi, GJ: AUTHOR [+2]

Abstract

This apparatus will indicate a missing control line 8 caused by failures in powering levels or in cable and board signal paths. Every time the binary triggers 10 see a positive transition, they will set to an opposite state. By arranging the control lines 10, the binary triggers 10 are always in step. It is possible to check with an exclusive OR circuit 12 for failure in a control line 8 during error sampling, by an AND gate 14 receiving the output of the exclusive OR circuit 12 at an error sampling time. The pulses indicate a sequence of signals on the lines 8.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Sequence Checking of Storage Control Line

This apparatus will indicate a missing control line 8 caused by failures in powering levels or in cable and board signal paths. Every time the binary triggers 10 see a positive transition, they will set to an opposite state. By arranging the control lines 10, the binary triggers 10 are always in step. It is possible to check with an exclusive OR circuit 12 for failure in a control line 8 during error sampling, by an AND gate 14 receiving the output of the exclusive OR circuit 12 at an error sampling time. The pulses indicate a sequence of signals on the lines 8.

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]