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Metal Insulator Semiconductor Structure for Impurity Profile Measurement

IP.com Disclosure Number: IPCOM000084105D
Original Publication Date: 1975-Sep-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Ogura, S: AUTHOR

Abstract

In the measurement of doping or impurity profiles of semiconductors, it is desirable to generate a plot of the profile by a direct and continuous type of measurement, with compensation to prevent measurement errors due to deep minority carriers.

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Metal Insulator Semiconductor Structure for Impurity Profile Measurement

In the measurement of doping or impurity profiles of semiconductors, it is desirable to generate a plot of the profile by a direct and continuous type of measurement, with compensation to prevent measurement errors due to deep minority carriers.

As indicated in Figs. 1 and 2, a test semiconductor structure is deposited on a test wafer having a substrate 1. The test structure has a semiconductive area 2 formed thereon by ion implantation or a similar method, and a very small diffused area 4 of the opposite conductivity type is deposited in the test area. A metallic contact 6 is deposited for contact with the gate 5, diffusion 4 and the substrate 1 sections.

The test sample 1 is connected to a capacitance bridge 7 which is connected to the gate and the substrate areas directly, and to the diffused area 4 through an inductance 8 between the diffusion and the substrate connections. The diffusion 4 is biased by a battery 9 to enable it to pick up the minority carriers generated in the semiconductor region 2, so that they do not interfere with the capacitive measurements. The capacity bridge 7 includes a bias control 10 to vary the bias voltage between the gate 5 and substrate 1.

In operation, the bridge 7 will measure the capacitance between the gate 5 and semiconductor 2 and will supply the value to a function generator 11, which will generate a signal representative of the rate of change of the...