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Ternary Full Adder

IP.com Disclosure Number: IPCOM000084107D
Original Publication Date: 1975-Sep-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Maholick, AW: AUTHOR [+2]

Abstract

The ternary full adder (Fig. 1) provides the modulo three sum of two ternary digits, A and B, and the CARRY output from the previous stage.

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Ternary Full Adder

The ternary full adder (Fig. 1) provides the modulo three sum of two ternary digits, A and B, and the CARRY output from the previous stage.

It consists of five ternary AND circuits, 1 to 5; two ternary OR circuits, 6 and 7; and eight unary function circuits, 8 to 15. The AND circuit has its output at the lesser of the two input signals, and the OR circuit has its output at the greater of the two input signals whenever the inputs are different.

The unary logic blocks function logically as shown in Figs. 2, 3, 4, 5, and 6, where a number in the logic block indicates that the input value passes through unchanged and the other two are interchanged. A right pointing arrow indicates that each input is incremented, modulo 3 and a left arrow indicates a similar decrementing.

The circuitry shown in Fig. 1 uses two ternary half-adders to implement the ternary full-adder function instead of a direct circuit implementation. The ternary half-adder shown in the upper portion of Fig. 1 implements the sum of two ternary digits in accordance with the logical function, F = A/0/B + A/1/B + A/2/B<- -. An alternate form of this function, not shown, is F = AB/0/ + A/-->/B/1/ + A/<-- /B/2/.

The second half-adder shown in the lower portion of Fig. 1 is simplified by realizing that the output carry from the previous stage is binary rather than ternary, since a carry output of 2 will not occur (i.e., it can take on values of 0 or 1 but not 2).

A direct implementation of...