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Test Points for Logic Checking

IP.com Disclosure Number: IPCOM000084129D
Original Publication Date: 1975-Sep-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 30K

Publishing Venue

IBM

Related People

Herrell, DJ: AUTHOR

Abstract

To check and verify correct operation of a general logic chip, it is desirable to provide strategically located test points throughout the circuit. For Josephson technology terminated line logic (TLL), such test points will generally take on the form of readout gates placed at suitable points in a general logic circuit.

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Test Points for Logic Checking

To check and verify correct operation of a general logic chip, it is desirable to provide strategically located test points throughout the circuit. For Josephson technology terminated line logic (TLL), such test points will generally take on the form of readout gates placed at suitable points in a general logic circuit.

It is proposed that all such test gates be serially connected and the individual gates selected using a decoding scheme. The suggested arrangement is shown schematically in Fig. 1.

In test circuit 1, test junctions are labelled J1 to J8. Consider that these junctions have a fan-in of four. One of the inputs, not shown, to each junction corresponds to the current of interest (generally an output current). The other three inputs control the decoding to select just one of the readout junctions J1-J8. With an inverter on the chip, the requirement will be for only five extra pins to be able to select up to eight test points, i.e.; Three pins for A, B or C inputs. Two pins for V(out).

The test gate supply current can be commoned to the general gate supply distribution on the chip and does not require independent pins. Using an extra pin, bringing the total to six pins, decoding into sixteen possible test points can be achieved.

Current waveforms can be monitored directly by varying the level of one of the input lines A, B, C used to decode and select a particular test point gate: that is, provided the test point gate design were such to ensure one-to-one correspondence of individual control lines and algebraic addition of the effects of currents in these control lines.

In additio...