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Regulated Power Supply for MTL Integrated Circuits

IP.com Disclosure Number: IPCOM000084142D
Original Publication Date: 1975-Sep-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 4 page(s) / 68K

Publishing Venue

IBM

Related People

Jaeger, RC: AUTHOR

Abstract

Described is a regulated power supply technique for Merged-Transistor Logic (MTL). The supply uses on-chip sensing circuits to control the regulated current or voltage which is supplied to the chip. The technique offers the advantage of maintaining the current drive to the MTL logic gate constant and independent of device parameter variations caused by processing. Also, the bulk supply voltage level to the regulator is minimized.

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Regulated Power Supply for MTL Integrated Circuits

Described is a regulated power supply technique for Merged-Transistor Logic (MTL). The supply uses on-chip sensing circuits to control the regulated current or voltage which is supplied to the chip. The technique offers the advantage of maintaining the current drive to the MTL logic gate constant and independent of device parameter variations caused by processing. Also, the bulk supply voltage level to the regulator is minimized.

The basic MTL logic gate is shown in Fig. 1. The PNP device 10 functions as a current source to supply the operating current to the MTL gate 12. Average gate delay is a function of the current flowing into the base of the NPN transistor, and a typical delay vs. current curve is shown in Fig. 2. In the low-current region, delay is directly proportional to the current level.

If the PNP device of Fig. 1 is supplied by a current source or resistor 14 as in Fig. 3, then the delay of the logic gate becomes dependent upon the PNP common-base current gain alpha, a poorly controlled device parameter. A closed-loop regulated supply with proper current sensing may be used to maintain constant base drive current to the logic gate.

A regulated voltage supply is shown in Fig. 4. Regulated voltage is supplied to the chip through pass transistor 16 which may be operated partially in saturation. Thus the bulk supply voltage V(B) may be only a few tenths of a volt above the required chip voltage, and power loss in the regulator is minimized. The regulated voltage is controlled by sensing the current flowing out of the PNP 18 collector at point A of the logic gate. A two-collector logic device 4 is connected to form an unity-gain current mirror.

The current I(c) is approximately equal to I(s) for reasonable values of NPN current gain. The cell current I(s) is controlled by comparing I(c) to the reference potential at...