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Browse Prior Art Database

Logically Hazard Free Polarity Hold Latch Layout

IP.com Disclosure Number: IPCOM000084225D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Heilwell, MF: AUTHOR [+2]

Abstract

This is an implementation of a polarity-hold latch on a logic masterslice integrated circuit chip, which minimizes the defective chips and provides fail-safe characteristics of certain failure mechanisms.

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Logically Hazard Free Polarity Hold Latch Layout

This is an implementation of a polarity-hold latch on a logic masterslice integrated circuit chip, which minimizes the defective chips and provides fail-safe characteristics of certain failure mechanisms.

Fig. 1 shows a polarity-hold, logically hazard-free latch constructed of NAND gates used in the logic design of electronic equipment. "Polarity-hold" means that the state of data presented to the latch is maintained by the latch after the in-gate clock is shut off. "Logically hazard-free" means that the latch is designed logically, so that glitches appearing on the latch outputs under the conditions of latch set/clock turnoff and latch set (second time in a row)/clock turnon are eliminated.

This characteristic, which makes the latch hazard-free, is a logical redundancy which also gives rise to an untestable stack-at-1 (SA1) fault occurring at point A. This fault in physical implementation has two main contributors: (1) An open in the metallization of the feedback to point A. (2) An open input transistor emitter contact at point A of the logically hazard-free gate.

The solution is depicted in Fig. 2, which illustrates only the circuits of interest:

Physically interconnect the logically hazard-free gate between the extend input, system data gate, scan data gate (if any) and the latch reset gate. This guarantees that any discontinuity in the collector dot will be detected by conventional DC stuck fault testing. This...