Browse Prior Art Database

Silicon Gate P Channel FET Fabricated Simultaneously with Bipolar Transistors

IP.com Disclosure Number: IPCOM000084232D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 113K

Publishing Venue

IBM

Related People

Antipov, I: AUTHOR

Abstract

This process results in a self-aligned, silicon gate P-channel field-effect transistor (FET) during the fabrication of NPN type bipolar transistors. One extra mask step, that of the gate, is all that is required.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 72% of the total text.

Page 1 of 2

Silicon Gate P Channel FET Fabricated Simultaneously with Bipolar Transistors

This process results in a self-aligned, silicon gate P-channel field-effect transistor (FET) during the fabrication of NPN type bipolar transistors. One extra mask step, that of the gate, is all that is required.

Fig. 1 illustrates a particularly fabricated NPN bipolar transistor up to the collector reach-through step. The device contains a N+subcollector region in a P-type substrate, N-epitaxial layer and P+ and SiO(2) isolation regions.

The mask which defines the base of the NPN transistors is also used to define the device areas of the P-channel FET's. The mask is used in removing the SiO2 from those areas where ion implanted N-type impurities are required by the P-channel gate FET, as shown in Fig. 2. The dosage is too low to affect the base region.

In the next steps the FET gate structure is formed, as shown in Fig. 3, by oxidizing the N-layer in the right-hand side of the drawing, depositing a layer of arsenic-doped polycrystalline silicon and oxidizing the polycrystalline silicon. Instead of oxidizing the polycrystalline silicon, a layer of silicon dioxide may be deposited by pyrolytic techniques. With the mask defining the gates, the SiO(2) and polycrystalline silicon are removed everywhere except in the gate region.

As shown in Fig. 4, the base region of the NPN transistor and the source and drain regions of the P-channel field-effect transistors are simultaneously formed by io...