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Glitchless T/2/L Latch Utilizing Single Phase Clock Input

IP.com Disclosure Number: IPCOM000084234D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Berndlmaier, E: AUTHOR [+3]

Abstract

The T/2/L latch circuit depicted performs the function of ZO = DC + C Zi. This function is generated without and output glitches.

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Glitchless T/2/L Latch Utilizing Single Phase Clock Input

The T/2/L latch circuit depicted performs the function of ZO = DC + C Zi. This function is generated without and output glitches.

With clock C and data D inputs both at an uplevel the voltage at the base of T1 is 2VF + 1VBE above ground, where VF is the forward voltage drop of a Schottky barrier diode. T1 is on and T2 is off, causing the base of T3 to rise to 1VF + 2VBE's above ground. This results in Zi and ZO both being at downlevels. ZO is at a voltage level of VBE - VF above ground. When the clock input returns to a downlevel, the base of T2 is held off maintaining the downlevel at the output.

With clock input up and data input down, the base of T1 is down and T1 is held off. This permits the base of T2 to rise to 2VF + 1VBE above ground and T2 conducts. This forces the base of T3 to a 2VF + 1VBE - 1VF level. T3 is held off which permits Zi and ZO to rise to uplevels. This voltage rise is aided by the active pull-up circuit of R9, T5, D9 and D10. ZO reaches V2 voltage level. The holding circuit for this state when the clock drops is maintained through T4, R5 and R2.

The output drive to T6 is determined by the current in R4 and R6 less that in R7. Voltage V1 may be set equal to V2.

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