Browse Prior Art Database

Bilevel Dual Impedance Monolithic Structure

IP.com Disclosure Number: IPCOM000084236D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Gani, VL: AUTHOR [+2]

Abstract

The structure and circuit described herein performs both as a Schottky diode logic gate for use at on-chip voltage levels and as a high-impedance PNP emitter-follower receiver for off-chip transmission line levels.

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Bilevel Dual Impedance Monolithic Structure

The structure and circuit described herein performs both as a Schottky diode logic gate for use at on-chip voltage levels and as a high-impedance PNP emitter-follower receiver for off-chip transmission line levels.

Fig. 1 shows one bilevel dual impedance (BLDZ) structure consisting of diode D1 and transistor T1. For use as an off-chip receiver, nodes 1 and 2 are open. The off-chip signal entering mode 3 is applied to the base of emitter-follower Tl, which offers a high impedance to this signal.

For use as an on-chip logic gate, nodes 1 and 2 are connected together by metallization, thus shunting the emitter-base junction of T1 with a Schottky barrier diode D1, whose low-forward voltage characteristics allow node 3 to accept on-chip logic levels.

A cross section of a BLDZ structure is shown in Fig. 2. A recessed-oxide insulator (ROI) defined Schottky barrier diode is formed in the conventional way with an N+ subcollector above a P- substrate, followed by N- EPI and tantalum metallization with a ROI guard ring. The N+ subcollector, however, extends beyond the ROI and into the base of the PNP transistor. The N+ reach-through thus becomes a common contact for the Schottky diode cathode and the PNP transistor base.

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