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Parity Check Circuit Arrangement for Random Access Memory Array

IP.com Disclosure Number: IPCOM000084238D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 67K

Publishing Venue

IBM

Related People

Marzin, C: AUTHOR [+2]

Abstract

Depicted in the drawings is a parity check circuit arrangement for a random-access memory array. As illustrated, the memory array has an output byte of nine bits and the parity flag output is 0 for an even number of binary 1's.

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Parity Check Circuit Arrangement for Random Access Memory Array

Depicted in the drawings is a parity check circuit arrangement for a random- access memory array. As illustrated, the memory array has an output byte of nine bits and the parity flag output is 0 for an even number of binary 1's.

Fig. 1 shows a two-input exclusive OR circuit which has low-power dissipation.

Fig. 2 depicts how the exclusive OR circuits performing the parity function are interconnected and connected to the memory array. The 0 through 8 inputs of the XOR circuits are connected to the array memory. Only the connection of input 0 is expressly shown in the drawing.

Each sense amplifier circuit includes transistors TA and TB, respectively, having their emitters connected to a discrete one of the pair of bit lines associated with the sense amplifier. One output (node A) of the sense amplifier is connected to the data-out driver. The other output (node B) of the sense amplifier is connected to an input of the XOR circuits.

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