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High Speed Glitchless Cascade Latch with Set

IP.com Disclosure Number: IPCOM000084240D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Blumberg, RJ: AUTHOR [+2]

Abstract

In many emitter-coupled logic (ECL) latches, in order to perform the latching function, the delay is a minimum of two logic blocks for positive data and a minimum of three logic blocks for negative data. This means that in general, latch delays are on the order of 3.0 to 4.5 nsec. By using a "cascade" type of circuit design, the latch delay can be reduced to one block of delay or approximately 1.5 nsec.

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High Speed Glitchless Cascade Latch with Set

In many emitter-coupled logic (ECL) latches, in order to perform the latching function, the delay is a minimum of two logic blocks for positive data and a minimum of three logic blocks for negative data. This means that in general, latch delays are on the order of 3.0 to 4.5 nsec. By using a "cascade" type of circuit design, the latch delay can be reduced to one block of delay or approximately 1.5 nsec.

The output state of the latch is allowed to change when the clock is negative. On the positive transition of the clock pulse, whatever data is present is locked into the latch. A change in the information present at the data input will not affect the output information when the clock is positive. With the clock positive, the set can go positive and lock a positive valve into the latch.

The operation of the cascade latch is as follows: Assume that the clock is negative which will turn off transistors TC1 and TC2. If data is positive TD1 will turn on, causing TR1 to turn off and VC node to rise to VCC voltage. If data is negative, TD1 will turn off and TR1 will turn on causing VC node to drop to a low level. Transistor TEF is an emitter-follower which is terminated at the end of the driven transmission line. With the clock negative, the VC node will be in phase with the data signal and hence the data will appear at the output node Zf.

A latched condition exists when the clock is positive with respect to VREF; under this c...