Browse Prior Art Database

Via Etch Control for Zero Overlap Vias

IP.com Disclosure Number: IPCOM000084255D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Mathad, GS: AUTHOR [+3]

Abstract

Etching interconnecting vias becomes very critical with high-density products with multiple layers of metal lines.

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Via Etch Control for Zero Overlap Vias

Etching interconnecting vias becomes very critical with high-density products with multiple layers of metal lines.

When metal lines are closely spaced, the interconnecting vias must be precisely etched because the lateral etching of a via could cause a short with an adjacent metal line. Since critical dimension changes occur at the end of the etching process, tolerance control can be improved by performing the etching process in two steps: 1) underetch the vias (Fig. 1) so that the vias are not opened completely as at 2; and 2) repeat the photoresist process (step 1) and then etch the remaining quartz (Fig. 2).

The photoresist process in Step 1 includes: apply and dry, expose, and via pattern develop. Also shown in Fig. 1 are the photoresist 4, a metal line 6, partial via 8, and quartz 10.

In the current, conventional process (Fig. 3), the entire etching i+ done in one step by overetching many vias on the wafer. While opening the vias over the thick quartz 10, the vias over the thin quartz are also overetched, which causes excessive lateral etching at such locations.

Underetching can result in unacceptable via-contact resistance. overetching can result in vias shorting with adjacent metal lines, or bringing the via wall so close to an adjacent metal line as to cause reliability problems.

The proposed solution makes the process insensitive to overetch, because no (or very little) lateral etching occurs during the second proce...