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Browse Prior Art Database

Level Shifting Circuit

IP.com Disclosure Number: IPCOM000084260D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Freeman, LB: AUTHOR [+3]

Abstract

This is a circuit for converting potential levels compatible with bipolar logic levels of transistor-transistor logic (TTL) to field-effect transistor (FET) logic levels.

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Level Shifting Circuit

This is a circuit for converting potential levels compatible with bipolar logic levels of transistor-transistor logic (TTL) to field-effect transistor (FET) logic levels.

It is known that TTL circuits typically have down logic levels distinguished from up logic levels by approximately 3 volts. Field-effect transistor circuits constructed in accordance with n-channel technology require a level shift in the order of 8.5 volts.

The circuit illustrated converts the bipolar logic levels of TTL technology to FET logic levels by the use of four field-effect transistors. Three of the field-effect transistors are depletion mode while the fourth is enhancement mode, as shown.

An important element in the illustrated circuit is the grounded-gate depletion mode device T1, which receives a downlevel logic input of 0 volts and an uplevel logic input of 3 volts. This 3 volt swing is sufficient to turn enhancement mode transistor T4 on or off, providing an inverted output voltage swing of 8.5 to 0.5 volts with a supply potential of 8.5 volts.

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