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Three Circuit Polarity Hold Latch

IP.com Disclosure Number: IPCOM000084261D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

DeSautels, JC: AUTHOR [+3]

Abstract

This is a latch circuit providing a latching function with fewer AND-INVERT (AI) logic circuits.

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Three Circuit Polarity Hold Latch

This is a latch circuit providing a latching function with fewer AND-INVERT (AI) logic circuits.

Fig. 1 shows a typical memory array driver. Each data line is common to a column of latches or storage elements. Address lines each gate a row of latches. A clock C is common to all latches in order to set or reset them at a given time.

Fig. 2 shows a typical four-circuit, polarity-hold latch used in the array. Four NAND (AND-INVERT) circuits clock and hold data. When the address line is active, the clock pulse gates a set or reset to the latch, depending on the data lines polarity. When the clock pulse ends, the data polarity that was at the latch is retained.

Fig. 3 illustrates the improved circuit which provides the same polarity-hold function as the circuit of Fig. 2, but requires only three NAND circuits (AI1, AI2, and AI3). Circuit AIA provides an address gated clock pulse to a row of latches. Circuits AIB and AIC provide delayed clock pulses to the entire latch array.

When the address line is active, the clock pulse applies a minus reset to the latch through circuit AIA. A delayed clock pulse through circuits AIB and AIC applies a minus set if the data line is positive. When the clock pulse falls, the latch reset is removed, followed by the set removal because of the added delay, leaving the latch set.

If the data line is negative when the clock pulse arrives, the reset is applied but the set is blocked, causing the latch to re...