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Trailing Edge Triggered Latch

IP.com Disclosure Number: IPCOM000084262D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

DeSautels, JC: AUTHOR [+3]

Abstract

This is a latch circuit that is reset by the trailing edge rather than the leading edge of a reset signal. A trailing edge triggered latch permits the last step (EXIT) of a sequence to complete before its signal resets a condition (cycle-steal latch) to be maintained through the sequence.

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Trailing Edge Triggered Latch

This is a latch circuit that is reset by the trailing edge rather than the leading edge of a reset signal. A trailing edge triggered latch permits the last step (EXIT) of a sequence to complete before its signal resets a condition (cycle-steal latch) to be maintained through the sequence.

In order to perform the reset function by the trailing rather than the leading edge of a pulse (+EXIT), the reset signal is applied to both the set and reset sides of the latch with a delay in the reset side. Therefore, the set is maintained (the "on" output) during the + reset pulse. At the end of the + reset (+EXIT) the set is removed, but the reset is retained by the delay path long enough to reset the latch.

At the time t1, the set input to AI5 is brought down, and the output goes up as shown in the waveform diagram. At t2, the initial set pulse switches positive but the output of AI5 does not change, because it is latched by an input from AI4. At t3, the output of AI5 is held positive by an input from AIl before AI4 can switch positive, causing the output AI5 to remain positive. At t4, the -set line switches positive allowing AI5 to switch negative while the delay retains -reset, which holds AI4 positive. The negative latch from AI5 then holds AI4 positive after - reset leaves, completing the reset of the latch.

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