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Parity Prediction for Incrementers

IP.com Disclosure Number: IPCOM000084264D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 1 page(s) / 12K

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Related People

Campbell, JE: AUTHOR [+2]


The present technique speeds up register update by predicting parity rather than generating it.

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This is the abbreviated version, containing approximately 62% of the total text.

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Parity Prediction for Incrementers

The present technique speeds up register update by predicting parity rather than generating it.

A known technique for generating parity is by passing all bits of a byte of information through exclusive OR circuits and then adding a parity value, such that odd or even parity is maintained. It has been noted that for counters or incrementers such conventional techniques for generating parity are not necessary. Because of the orderly way in which the data changes in a counter or incrementer, it is possible to predict the parity of the "new" value from the "old". Thus, parity can be generated during the update of the data and it is not necessary to wait for the completion of an operation.

The algorithm for predicting parity can be expressed as follows: parity (old) = parity (new) unless an odd number of the lowest order bits are all 1's immediately preceded by at least one high-order 0, or unless an even length field is "wrapping around" from all 1's to 0's. For a

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byte of data, parity (old) = parity (new) except when data = 00000001, 00000111, 00011111, 01111111, 11111111. In a half-word counter, the same conditions are checked for the high byte, and together with the condition that the low byte is all 1's are passed through an AND circuit. This algorithm can be extended to incrementing by any power of 2, by considering the bit representing that particular power of 2 as the lowest order bit in checking conditions on...