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Tracking Analog To Digital Converter Ripple Elimination

IP.com Disclosure Number: IPCOM000084305D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Lavallee, RW: AUTHOR

Abstract

A basic tracking analog-to-digital (A/D) converter is shown within the dash-line block 10 of Fig. 1. This converter operates by comparing the analog voltage from the DAC (digital-to-analog converter) 12 with the analog voltage input in comparator 14. It will be appreciated that the output of the comparator 14 can be plus or minus, depending on the relative comparison of the two inputs.

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Tracking Analog To Digital Converter Ripple Elimination

A basic tracking analog-to-digital (A/D) converter is shown within the dash- line block 10 of Fig. 1. This converter operates by comparing the analog voltage from the DAC (digital-to-analog converter) 12 with the analog voltage input in comparator 14. It will be appreciated that the output of the comparator 14 can be plus or minus, depending on the relative comparison of the two inputs.

This output from the comparator 14 sets or does not set a latch 16, thus producing an up or down output depending on the latch condition. The up or latch condition equals a 1 and the no latch or down condition equals 0. This output from latch 16 increments an up or down counter 18 accordingly. The count in the counter 18 can be utilized as an output and is also utilized as the input to the DAC 12. The corresponding analog voltage from the DAC 12, as previously mentioned, forms one of the inputs to the comparator 14.

The normal A/D (analog-to-digital) converter output is shown in Fig. 2. This consists of a least-significant bit (LSB) ripple even when the input is not changing. This ripple is undesirable in some applications such as in graphics terminals which have digitally addressed displays, but whose input vectors (X-Y coordinates) may be analog voltages as functions of time. The undesired ripple may be eliminated by effectively averaging the up/down decision over a period consisting of each pair of adjacent conversion cycl...