Browse Prior Art Database

Data Transfer Under Microinstruction Control

IP.com Disclosure Number: IPCOM000084309D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Ovrebo, JD: AUTHOR [+2]

Abstract

Data transfer for a disk storage drive is improved by having the same microinstruction which controls the data transfer also reset the interrupt, and thereby eliminate the need for an additional microinstruction. In the past, one byte of data was transferred in a dedicated mode without allowing any time for system processing. In the present arrangement, only a portion of the time interval between available bytes is used for data transfer and the remaining portion is available for system processing.

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Data Transfer Under Microinstruction Control

Data transfer for a disk storage drive is improved by having the same microinstruction which controls the data transfer also reset the interrupt, and thereby eliminate the need for an additional microinstruction. In the past, one byte of data was transferred in a dedicated mode without allowing any time for system processing. In the present arrangement, only a portion of the time interval between available bytes is used for data transfer and the remaining portion is available for system processing.

In this particular example, one byte of data is transferred every 32 mu secs. Of the 32 mu sec interval, 12.4 mu secs are used for data transfer and thus 19.6 mu secs are available to the central processing unit for system processing.

In Fig. 1, the data transfer is initiated by a microinstruction which generates an Enable 32 mu sec INTR signal. This signal resets counter 10 and INTR REQ LVL1 latch 30 and sets ENABLE 32 mu sec INTR latch 15. Counter 10 is advanced by a 2 mu sec pulse and upon reaching a count of 32 mu secs, it provides a signal to AND circuit 11. AND circuit 11 has been conditioned by latch 15 and thus passes the signal from counter 10 to set latch 30. With latch 30 set, an interrupt request is sent to the central processing unit.

When the central processing unit grants the INTERRUPT LEVEL 1 request, a program loop, Fig. 2, starts. The first step of the loop is to store the program condition register (PCR)....