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Emitter Noise Filter

IP.com Disclosure Number: IPCOM000084311D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Schmitt, SA: AUTHOR

Abstract

A filter circuit utilizes latches having a set input which overrides the reset input. The filter is particularly suited for an emitter generating a pair of signals 90 degrees out-of-phase.

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Emitter Noise Filter

A filter circuit utilizes latches having a set input which overrides the reset input. The filter is particularly suited for an emitter generating a pair of signals 90 degrees out-of-phase.

The filter circuit shown in Fig. 1 receives raw emitter signals A and B shown in Fig. 2. Latches A, B, C and D are initially reset by a start signal. The leading edge of the raw emitter A pulse sets latch C via AND circuit 10. The raw emitter B pulse then sets latch D via AND circuit 20. The output of AND circuit 20 is also connected to reset latch C; however, the set input signal from AND circuit 10 holds latch C set until raw emitter pulse A drops. When this occurs, latch C resets and latch A sets via inverter 11 and AND circuit 12. Also, inverter 13 provides a reset to latch D. Latch D, similar to latch C, remains set until raw emitter B drops.

The output of latch A inhibits AND circuit 10 so as to prevent a noise pulse on the trailing edge of raw emitter pulse A from setting latch C. It should also be noted that raw emitter pulse B must be present in order for latch A to be set. Hence, a noise pulse on the leading edge of the raw emitter A pulse can set latch C, but when it drops it cannot set latch A because raw emitter pulse B does not occur until 90 degrees later.

Latch A is reset via inverter 21 when the raw emitter pulse B drops. When this occurs, latch B is set via AND circuit 22. Also, since raw emitter pulse B is no longer holding latch D set, i...