Browse Prior Art Database

Low Performance Cycle Steal Priority

IP.com Disclosure Number: IPCOM000084313D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 77K

Publishing Venue

IBM

Related People

Duggan, CJ: AUTHOR

Abstract

A multiple class cycle steal system is described in the IBM Technical Disclosure Bulletin, Vol. 17 No. 10, March 1975, pages 2992 to 3001. In order for multiple I/O devices to utilize the low performance (base cycle steal) cycle steal mode, it is necessary to have cycle steal priority among the I/O devices. Low performance or base cycle steal priority of the multiple I/O devices is achieved by the I/O devices themselves. This is accomplished by priority circuity which forces bits onto Data Bus Out (MPXPO), which cause the lower priority I/O devices to ignore the cycle steal.

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Low Performance Cycle Steal Priority

A multiple class cycle steal system is described in the IBM Technical Disclosure Bulletin, Vol. 17 No. 10, March 1975, pages 2992 to 3001. In order for multiple I/O devices to utilize the low performance (base cycle steal) cycle steal mode, it is necessary to have cycle steal priority among the I/O devices. Low performance or base cycle steal priority of the multiple I/O devices is achieved by the I/O devices themselves. This is accomplished by priority circuity which forces bits onto Data Bus Out (MPXPO), which cause the lower priority I/O devices to ignore the cycle steal.

I/O device attachments 10, 20 and 30 for I/O devices 0, 1 and 2 are shown in block form in Fig. 1. Each of these I/O device attachments correspond to I/O device attachment 50 shown in the above referred to publication, except as modified to provide priority. All of the signals to and from attachment 50 would also apply to attachments 10, 20 and 30, except that the Cycle Steal Request signal to Port 0 comes from attachment 20 and Cycle Steal Request signals from attachments 10 and 30 feed into attachment 20. Only the Cycle Steal Request lines and MPXPO lines are shown in Fig. 1. The MPXPO lines are shown in two groups rather than a single bus to illustrate the priority arrangement. Logic circuitry in Fig. 2 forces bits 0-2 onto MPXPO bits 0-2.

Cycle Steal Requests for I/O device attachments 10, 20 and 30 are applied to OR circuit 22, Fig. 2, over lines 11, 21 and 31. The output of OR circuit 22 is applied over line 40 as a Cycle Steal Request signal to Port 0, not shown. The Cycle Steal Request signals on lines 11, 21 and 31 are also applied to priority logic including inverters 23 and 32, AND circuits 24 and 25 and latches 26, 27 and 28. These latches are reset by a System Reset signal and by a -Control Out Signal. The -Control Out Signal inverted by inverter 29 is applied to the clock input or latches 26, 27 and 28.

Only one of the latches 26, 27 and 28 will be set upon receiving the clock signal from inverter 29. The Q output of latch 26 is connected to reset inputs of latches 27 and 28. Hence, if latch 26 is set, it prevents latches 2...