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Statistical Digital Data Separator

IP.com Disclosure Number: IPCOM000084314D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Miller, TH: AUTHOR [+2]

Abstract

A statistical digital data separator is provided for separating bits contained in raw digital data coming from a transducer, after the raw data has been shaped, amplified and clipped. A significant feature of this data separator is its ability to handle data which had been recorded by either FM or MFM techniques. Normally data separators for MFM data require less bit shift, and thus different separators were required according to the type of recording.

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Statistical Digital Data Separator

A statistical digital data separator is provided for separating bits contained in raw digital data coming from a transducer, after the raw data has been shaped, amplified and clipped. A significant feature of this data separator is its ability to handle data which had been recorded by either FM or MFM techniques. Normally data separators for MFM data require less bit shift, and thus different separators were required according to the type of recording.

Waveforms for FM and MPM data are shown in Fig. 1. The shaped, amplified and clipped raw digital data for either type of recorded data is sampled ten times per sample period, and the resulting bits are fed via line 11 into register
10. Register 10 is a ten-bit register and the right hand five bits representing the next bit to be determined, are initialized at phase B time of every sample period to 00001 by line 12.

The sixth position of register 10 is connected to set lst one latch 15. The one bit forced into register 10 at phase B time is shifted through register 10 by carry or overflow pulses from counter 20 via line 21. Thus latch 15 is initially set after register 10 has been shifted five times. Latch 15 is reset by a phase C signal.

Counter 20 is initialized by a signal on line 22 and is loaded with a value related to speed from sample counter 30, under control of a signal from AND circuit 40. Counter 20 is advanced by 100 nanosecond pulses from clock 50. AND circuit 40 is fed by the output of latch 15 and gated by a phase B signal from clo...