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Memory Compatible Logic Scheme for Josephson Tunneling Memories

IP.com Disclosure Number: IPCOM000084336D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 27K

Publishing Venue

IBM

Related People

Herrell, DJ: AUTHOR [+3]

Abstract

Consider the circuit of Fig. 1, which has the form of the terminated logic scheme shown in U. S. Patent, 3,758,795, issued September 11, 1973 in the name of Anacker et al. In the patent, Z(s)>>Z(o) and R=2Z(o). The present circuit shows a gate design wherein R<2Z(o) and Z(s)=Z(o) or Z(s)>Z(o).

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Memory Compatible Logic Scheme for Josephson Tunneling Memories

Consider the circuit of Fig. 1, which has the form of the terminated logic scheme shown in U. S. Patent, 3,758,795, issued September 11, 1973 in the name of Anacker et al. In the patent, Z(s)>>Z(o) and R=2Z(o). The present circuit shows a gate design wherein R<2Z(o) and Z(s)=Z(o) or Z(s)>Z(o).

By a suitable choice of the impedance values R, Z(o) and Z(s), good isolation between gates can be achieved, while still keeping a relatively fast logic gate. In addition, a self-resetting mode can be exploited, yielding an even better isolation than that using an externally timed gate supply.

Consider first the propagation of an output signal from gate J(1) to readout gate J(2) in Fig. 2, initiated by depressing I(max) of J(1) by the necessary input on the control lines C(1).

Since Z(o)>R, to a good approximation, Z(o) can be replaced with its equivalent inductance. Let L(o) = inductance per unit length of line of impedance Z(o). Then; L(out) = 2l(o)D(o)Z(o) (1) where the factor of 2 brings in both legs (A and B) of the output. Now L(o)=D(o)Z(o), where D(o) is the delay per unit length, hence (1) can be written as; L(out) = 2l(o)D(o)Z(o) (2).

The output current i(t) tends (initially) to a current value of 2 delta/R with a time constant of L(out)/R, where 2 delta is the gap voltage. Thus the time constant is;

Tau = L(out) over R = 2l(o)D(o)Z(o) over R (3)

Using the following parameters, with SiO insulation; D(o) = 0.2pS/mil

Z(o) = 1 omega

l(o) = 20mils

R = 0.4 omega (to achieve a unit control current of;

i = 2 delta over R = 2.5 over 0.4 = 6.25mA),

Substituting in (3), tau = 2x20x0.2x1 over 0.4 = 20pS.

Thus, a 10% to 90% time of 50pS - which is very reasonable, can be obtained. Assume a longer output line of l'(o) = 50 mils, tau = 50pS and a 10% to 90% of = 125pS can be obtained.

The isolation problem may be simplified to consideration of only the adjacent gate circuit, where the circuit shown in Fig. 3 can be assumed. Disregarding the delay introduced by Z(1), it is seen that the disturb signal injected into this adjacent gate circuit upon switching of gate J3 can be considered as two counterrotating current wavefronts of delta/Z(o).

At any point in this adjacent circuit, the signals delta/Z(o), 0 or -delta/Z(o) appear as the disturb current depending on the position and relative arrival times of the two wavefronts, as measured...