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Device Process for Raised Junction MOSFET

IP.com Disclosure Number: IPCOM000084342D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Rideout, VL: AUTHOR

Abstract

Fig, 1 shows an idealized raised junction metal-oxide semiconductor field- effect transistor (MOSFET) which has several advantageous features such as: (1) The junctions are raised above the plane of the active channel region of the device, thus the associated depletion regions are reduced in extent relative to the channel. This reduces short-channel effects. (2) Isolation oxide exists alongside of and above the n+ junction regions, thus reducing sidewall capacitance. (3) The n+ junctions can be made quite thick, thereby reducing the sheet resistance of the lines (this is particularly important for logic circuits, especially those of the Weinberger layout type). (4) The source and drain are self-aligned with respect to the gate region.

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Device Process for Raised Junction MOSFET

Fig, 1 shows an idealized raised junction metal-oxide semiconductor field- effect transistor (MOSFET) which has several advantageous features such as:
(1) The junctions are raised above the plane of the active

channel

region of the device, thus the associated depletion regions

are reduced in extent relative to the channel. This reduces

short-channel effects.
(2) Isolation oxide exists alongside of and above the n+

junction

regions, thus reducing sidewall capacitance.
(3) The n+ junctions can be made quite thick, thereby

reducing the

sheet resistance of the lines (this is particularly important

for logic circuits, especially those of the Weinberger layout

type).
(4) The source and drain are self-aligned with respect to the

gate region.
(5) The channel implant and the field implant exist only

under their

respective oxides, and not under the n+ regions.
(6) The structure is highly planar at the final level.

A process for the fabrication of raised junction MOSFETS is described hereinafter. Figs. 2A through 2E illustrate the fabrication technique. A low temperature n+ layer is epitaxially grown on a p-type Si substrate of 2-10 ohm- cm resistivity. A thin oxide layer is grown or deposited to act as a mask for the field oxide regions. Photoresist is then applied and the thick field-oxide pattern is delineated.

The n+ regions are etched down to the p-type substrate. Etching control can be enhanced by use of a preferential electrochemical etching technique, which will stop when the p-type substrate is reached. To control undercutting, an anisotropic etchant such as hydrazine, pyrocatechol, or potassium hydroxide can be used. A Plasma etch such as carbon tetrachloride can also be used.

The field implant is then performed in the etched areas. The n+ region and its pro...