Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

High Performance Input Stage for Integrated Operational Amplifiers

IP.com Disclosure Number: IPCOM000084375D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Jaeger, RC: AUTHOR

Abstract

Fig. 1 shows an operational amplifier input stage 100 having high-gain, low-input bias current, high common-mode rejection ratio, high common-mode input resistance with low capacitance, and large input voltage ranges in both common and differential modes. It also has an offset null capability and requires a small number of resistive elements.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 77% of the total text.

Page 1 of 2

High Performance Input Stage for Integrated Operational Amplifiers

Fig. 1 shows an operational amplifier input stage 100 having high-gain, low- input bias current, high common-mode rejection ratio, high common-mode input resistance with low capacitance, and large input voltage ranges in both common and differential modes. It also has an offset null capability and requires a small number of resistive elements.

Stage 100 uses dual differential-cascode circuits biased by Wilson current sources to achieve high common-mode input impedance and rejection ratio. Transistor current source Q111-Q113 biases differential-cascode transistor circuits Q121-Q124 and Q131-Q134 having common diodes D11-D16. Low-input bias is obtained by using conventional "super-Beta" transistors Q122 and Q124 for receiving the differential input voltages V1 and V2.

High-input voltages are accommodated in spite of the low-breakdown characteristics of Q122 and Q124 by bootstrap transistors Q121, Q131, Q123 and Q133. Transistor current source Q141-Q143 requires only a single resistor R11 for setting the bias current of Q132 and Q134. Transistor current mirror Q151-Q153 provides a high impedance active load for the output voltage V0. Offset nulling is accomplished by unbalancing tail resistors R12 and R13 with potentiometer R14.

Fig. 2 shows a similar input stage 200 using integrated junction field-effect transistors (JFETs) Q222 and Q223 for low-input bias current in cascode transistor circuits Q221...