Browse Prior Art Database

Recessed Oxide One Device Cell FET Structure

IP.com Disclosure Number: IPCOM000084408D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Garnache, RR: AUTHOR

Abstract

The one-device cell structure taught by Garnache and Smith in United States Patent 3,841,926 is improved, by using a recessed oxide area and intermittently forming the active one-device cell.

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Recessed Oxide One Device Cell FET Structure

The one-device cell structure taught by Garnache and Smith in United States Patent 3,841,926 is improved, by using a recessed oxide area and intermittently forming the active one-device cell.

The process comprises forming, by any suitable known techniques, such as etching recessed channels in a silicon semiconductor substrate. These channels are oxidized and upon the area between the channels is formed a composite SiO(2) and Si(4)N(3) insulating layer. A channel stopper by implantation or any other suitable technique is provided. Within the recessed channel areas is provided about 5000 angstroms of SiO(2).

A polysilicon field plate is formed next adjacent one of the recessed channels to form a structure having the channels planar, one of which has a juxtapositioned polysilicon field plate.

The next procedural steps are to provide a source and drain diffusion and a self-aligned metal-oxide semiconductor (MOS) transistor by first etching the nitride and depositing a doped oxide, and by using conventional photolithography position the doped oxide in the desired pattern in the area where the source and drain diffusion is desired. The dopant is formed therebetween. The obvious steps of forming the contact holes, applying, and delineating the metal patterns are provided.

This process results in a significantly smaller cell than the conventional recessed oxide method.

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