Browse Prior Art Database

Producing Single Device Cell Structures

IP.com Disclosure Number: IPCOM000084409D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Garnache, RR: AUTHOR

Abstract

United States Patent 3,841,926 Garnache and Smith teaches a method for the manufacture of high-density, one-device integrated circuits with multiple conducting layers, such as polycrystalline silicon field shield and metal interconnection lines.

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Producing Single Device Cell Structures

United States Patent 3,841,926 Garnache and Smith teaches a method for the manufacture of high-density, one-device integrated circuits with multiple conducting layers, such as polycrystalline silicon field shield and metal interconnection lines.

The fabrication technique taught below is a method for producing a one- device cell using a new approach for producing a self-aligned field effect transistor (FET) structure in conjunction with surface-charge control, by use of built-in negative charge in an SiO(2)-Al(2)O(3)-SiO(2) field structure.

This is accomplished by modifying the method of the above patent by first growing a layer of 50-100 angstroms of SiO(2) on a silicon substrate, followed by the deposition of Al(2)O(3) and SiO(2) in about 200 angstroms and 1000 angstroms thick, respectfully. Standard photolithography etches the appropriate patterns of SiO(2) and Al(2)O(3).

The gate oxide is then grown followed by the deposition of intrinsic polysilicon of about 1000 angstroms. Masking and etching of the polysilicon is followed, after which doped oxide is deposited for drive-in of a dopant to form source and drain regions.

The gate windows are then formed and the dopant driven into the substrate desired regions. An appropriate gate structure is then established followed by conventional further processing.

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