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High Density Single Device Memory Cell with Minimized Parasitic Leakage

IP.com Disclosure Number: IPCOM000084410D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Bhattacharyya, A: AUTHOR [+4]

Abstract

Illustrated is a semiconductor cell vertical structure having minimized or no parasitic leakage.

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High Density Single Device Memory Cell with Minimized Parasitic Leakage

Illustrated is a semiconductor cell vertical structure having minimized or no parasitic leakage.

A monocrystalline silicon substrate is provided with a field-effect transistor (FET) structure thereon, having diffused source and drain regions 2 with a composite layer of SiO(2) and Al(2)O(3) illustrated at 3, and the insulating layer of SiO(2) in the region of 4.

The gate area passivation at 8 is composed of SiO(2) accomplished by thermally oxidizing the silicon after etching out previously deposited SiO(2)- Si(3)N(4) composite insulation, which continues to remain in the area at 5.

The deposition of polysilicon is provided at 6 and oxidized to form the oxide layer 7. A metal deposition of contact metallurgy, such as copper-aluminum or chromium-copper-gold is formed and illustrated at 9.

This structure provides two different field shield structures side by-side in the cell, alumina-oxide composite in the area along the gate edge and a polysilicon field shield in the areas surrounding the storage nodes.

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