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Field Effect Transistor Circuit

IP.com Disclosure Number: IPCOM000084414D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 22K

Publishing Venue

IBM

Related People

Moore, RL: AUTHOR

Abstract

This circuit avoids carrier injections into transistor gate insulators, particularly, dual-insulation layers such as silicon dioxide - silicon nitride, which can cause permanent alterations in field-effect transistor characteristics, by impressing an intermediate voltage VI prior to the application of a high-voltage VH to a transistor when turning it on.

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Field Effect Transistor Circuit

This circuit avoids carrier injections into transistor gate insulators, particularly, dual-insulation layers such as silicon dioxide - silicon nitride, which can cause permanent alterations in field-effect transistor characteristics, by impressing an intermediate voltage VI prior to the application of a high-voltage VH to a transistor when turning it on.

The voltage VI, which may be approximately one half of VH, is applied to transistors T1, T2, and T3 at node A by momentarily pulsing the gate electrode of transistor T4. Transistors T1, T2, and T3 are turned on by applying a positive pulse R to their gate electrodes. Pulse R is also applied to a relatively large transistor T5 to charge node A to one voltage threshold below VH, assuming the magnitude of pulse R to be VH. The size of T5 is chosen such that it charges node A slightly slower than T1, T2, and T3 charge their respective loads CL.

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