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High Density, Self Aligned Interconnection for Silicon Semiconductor Technology

IP.com Disclosure Number: IPCOM000084421D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Bhattacharyya, A: AUTHOR [+2]

Abstract

Referring to the drawings and Fig. 1 a self-aligned ohmic contact is made to the semiconductor diffusions and substrate where a substrate 1 with diffused regions 2 and 3 are provided.

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High Density, Self Aligned Interconnection for Silicon Semiconductor Technology

Referring to the drawings and Fig. 1 a self-aligned ohmic contact is made to the semiconductor diffusions and substrate where a substrate 1 with diffused regions 2 and 3 are provided.

The interconnections are made in the following sequences using known technology. First a thin-metal film 4 such as platinum or platinum chromium is selectively evaporated into the openings. This is followed by depositing a layer of thicker metal 5 superimposed upon the first metal layer 4 surrounded by a previously deposited insulator 7, such as SiO(2) or Al(2)O(3), in the form of either interconnecting lines 5A and/or contact pads 5B.

Contact pad 5B is protected by an appropriate masking technique while selectively oxidizing a portion of the metal layer 5 at 5A, to form an insulator around 5A shown at 6. The final layer of interconnection metallurgy 8 is provided to connect at 5B.

The aforesaid technique can be utilized to form a field plate 9 which is insulated by a thin dielectric 10, which is deposited over a silicon diffusion shown at 11.

Referring to Fig. 2, an alternate interconnection method is illustrated wherein subsequent to the deposition of the thick-metal layer 5 in Fig. 1, a selective deposition of silicon 12 over the interconnecting lines 5A of Fig. 1 was made, while protecting the metal pad 5B with an appropriate mask. The contact pad 5B is temporarily protected by an appropriate oxidiza...