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Platinum Gate FET Structure

IP.com Disclosure Number: IPCOM000084423D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Joshi, ML: AUTHOR [+3]

Abstract

The silicon field-effect transistor (FET) platinum gate structure formed in accordance with the following process provides for formation of gate oxide insulation under the platinum gate metal, by conventional oxidation forming an underlaying SiO(2) layer through the platinum and suitable metal, such as zirconium or titanium, used to aid in the adherence of the platinum to the silicon.

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Platinum Gate FET Structure

The silicon field-effect transistor (FET) platinum gate structure formed in accordance with the following process provides for formation of gate oxide insulation under the platinum gate metal, by conventional oxidation forming an underlaying SiO(2) layer through the platinum and suitable metal, such as zirconium or titanium, used to aid in the adherence of the platinum to the silicon.

In order to produce the structure illustrated in the figure, a monocrystalline silicon substrate 1 has diffused source and drain region 2 and 3 and a gate area
4. Associated therewith is an underlaying SiO(2) gate oxide layer 5 formed through a metallic adherence layer 6, a layer of platinum gate contact metal 8 and conventional metal 7 for outside contact.

A conventional FET processing sequence of steps are undertaken, except that it should be emphasized the gate insulating oxide 5 formed under the platinum 8 and adhesion metal 6 is accomplished by using standard oxidization techniques, to form the desired gate insulating oxide thickness through the platinum gate metal 8 and adherence promoting metal 6. Platinum in excess of 4500-5000 Angstroms thick will prevent further oxidation beneath the gate metal and adhesion promoting metal, such as titanium and the like.

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