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Redundant Bit Line Decode Circuit

IP.com Disclosure Number: IPCOM000084426D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Chu, JL: AUTHOR [+2]

Abstract

This redundancy circuit provides a technique for steering information to or from one or more redundant bit lines in an integrated circuit memory system.

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Redundant Bit Line Decode Circuit

This redundancy circuit provides a technique for steering information to or from one or more redundant bit lines in an integrated circuit memory system.

A redundancy decoder 10, responsive to storage address register (SAR) inputs SAR 1 to SAR N, is coupled to each redundant bit line 12 or a normally decoded bit line of memory array 14 via a one out of N decoder. Programming of decoder 10 is provided by a plurality of fusible links F associated with each input to decoder 10. As shown, decoder 10 will normally select redundant bit line 12 if all fuses are intact and all SAR inputs are true.

Any one of the normally decodable address inputs SAR may be selectably disabled by proper programming of fuses F. For example, if all fuses F are blown, then the address SAR = 1, or address zero, will select redundant bit line 12, while all other addresses will be decoded normally. Each redundancy decoder 10 is a NAND gage comprising a series of comparators controlled by fuses F.

Redundancy decoder 10 operates as follows. Prior to the beginning of a memory cycle, restore pulse R turns on field-effect transistors (FET's) T13 and T14. If fuse F is intact the gates of T16 and T15 will remain at ground and the gate of T11 will be charged. At the same time, pulse R precharges voltage node C, the output of decoder 10, thus enabling T3 and T5.

At the beginning of a memory cycle chip select pulse CS rises and is coupled to the gate of T7 through capacit...