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Directly Decoded Buffer Directory for Two Level Memory Hierarchy

IP.com Disclosure Number: IPCOM000084427D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

White, KR: AUTHOR

Abstract

This buffer memory directory provides a reduction in time and hardware required to perform the directory function in a two-level hierarchy memory system.

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Directly Decoded Buffer Directory for Two Level Memory Hierarchy

This buffer memory directory provides a reduction in time and hardware required to perform the directory function in a two-level hierarchy memory system.

Computer memory systems, including a small high-speed cache, or buffer, storage unit, in combination with a large slower backing, or main, store are conveniently utilized to improve memory performance at reasonable cost. In such systems, a relatively small extent of addressable storage space is stored in the high-speed buffer, with the expectation that a large proportion of memory activity can be directed to the buffer storage unit. When a main store address is accessed, which is not resident in the buffer, a slower main store memory cycle is required in order to gain access to the storage location.

In order to determine whether a main store address is resident in the buffer, a buffer directory containing the addresses of all main store address space resident in the buffer must be searched prior to initiation of either a buffer or a main store access cycle. This buffer directory utilizes conventional, high-speed semiconductor memory array chips to implement a main store address search of the buffer contents.

A typical two-level memory hierarchy might include a main store having a capacity of one megabyte, organized into eight classes, having 512 books each. Each book is a transferable unit of 256 bytes. The buffer has a capacity of 16 kilobytes, organized into eight classes. Any one of the 512 books within a particular class may be placed in any one of eight buffer "slots". Control logic in the buffer directory provides for replacement of the Least-Recently Used (LRU) mainstore address in the buffer, when all of the buffer slots within a particular class have been filled.

The buffer directory includes four local store chips: 10, 12, 14, and a chip 4 which is not shown; and control logic: OR circuit 18, encoder 20, logic update circuit 22, and wire dot OR 24, Positive logic is assumed. A storage address register (SAR), not shown, provides a main store address comprising twelve address bits (three class bits, and nine book bits) to local store chips 1, 2 and 3. The class address bits are provided to all three chips, while the book address bits are partitioned such that bits 0, 1 and 2 are applied to local store chip 1, bits 3, 4, and 5 to local store chip 2, and bits 6, 7, and 8 to local store chip 3. The six address bits provided to each chip are decoded one of 64 to provide an eight-bit data output signal S1---S8.

Comparison of the main store address with addresses stored in the directory is performed as follows. Initially, a "1" (high-level logic signal) is written into all storage locations of local store chips 1, 2, and 3. The application of a class and partial book address and a select signal causes eight "1"'s to be r...