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Browse Prior Art Database

Read and Write for Random Access Memory Array

IP.com Disclosure Number: IPCOM000084466D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Hsieh, JC: AUTHOR

Abstract

This is a technique for reading and writing into a random-access memory utilizing separate common bit lines.

This text was extracted from a PDF file.
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Read and Write for Random Access Memory Array

This is a technique for reading and writing into a random-access memory utilizing separate common bit lines.

In the figure, there is shown a memory matrix having 8 cells (C1 to C8) in a row and Y cells arranged in a column for an 8 X Y memory matrix. In order to select a data bit from the matrix, a downlevel select (S) pulse turns on the P- channel devices to which it is connected permitting the potential V to charge all the bit lines. The S pulse is then brought to an uplevel turning the P-channel devices to which it is connected off, permitting reading or writing from the selected cell.

During a read operation one of the word lines such as WL1 connects all the cells in that row to the associated column conductor bit lines. This causes a slight voltage difference between each pair of bit lines, due to the current flow from one of the pair of bit lines into the cell. One of the cell read pulses (CR1 to CR8) is also brought to a downlevel, transferring the potential difference on the column conductors to the read common bit-line conductors 10. This is sensed by the sense latch and outputted through the final latch. Note that during a read operation all the cell write circuits (CW1 to CW8) are maintained at a downlevel, keeping the write common bit lines 20 disconnected from the cells and the read circuits.

In order to write into the cell, all the chip read circuits are maintained off while one of the chip write circuit...