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Browse Prior Art Database

Wafer Voltage Distribution

IP.com Disclosure Number: IPCOM000084467D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Johnson, AH: AUTHOR

Abstract

A major problem in using wafers for logic or memory is distribution of high currents for voltages and ground, since the number and conductivity of the layers of device metallurgy are very limited. One approach is to run relatively long wires over the surface of the wafer to multiple pad locations. The disadvantage of this approach is the vulnerability of such long wires to damage. Also at the present is the problem in bonding wires that are relatively large in cross-sectional area due to their length, and the interference they present to surface probing or repair chip attachment.

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Wafer Voltage Distribution

A major problem in using wafers for logic or memory is distribution of high currents for voltages and ground, since the number and conductivity of the layers of device metallurgy are very limited. One approach is to run relatively long wires over the surface of the wafer to multiple pad locations. The disadvantage of this approach is the vulnerability of such long wires to damage. Also at the present is the problem in bonding wires that are relatively large in cross-sectional area due to their length, and the interference they present to surface probing or repair chip attachment.

The proposed solution to the problem is to provide a voltage distribution system directly under the wafer 1. This system would have appropriate dimensioned planes (such as copper) and would not have the constraints required of wiring planes in the semiconductor wafer. Connection to the wafer 1 can be by making connection through holes 2 placed in the wafer 1 by techniques such as TC bonding wires 3 to pads on the voltage distribution system, and pads on the wafer 1 leading to the ground or voltage area of the wafer being serviced by that connection.

Since the wire length is very short, it represents a short path not referenced to ground and can be made of small diameter wire because the voltage drop will be small compared to a longer surface wire. The holes 2 can be put in the wafer 1 by a variety of techniques at and after any stage of wafer processing.

The vo...