Browse Prior Art Database

Single Electrode Double Threshold Device

IP.com Disclosure Number: IPCOM000084469D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Ho, IT: AUTHOR [+2]

Abstract

In the publication Single-Electrode One-Device Cell appearing in the IBM Technical Disclosure Bulletin, Vol. 15, No. 6, November 1972, pages 1765 and 1766, a single-device cell is described of the single field-effect transistor (FET) type, in the class of cells described in U. S. Patent No. 3,387,286. In the above-published article, the gate electrode and capacitor ground plate electrode are combined into a single electrode to provide a memory array cell with fewer metal connections and a higher packing density. In the cell shown, the N substrate is biased to ground.

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Single Electrode Double Threshold Device

In the publication Single-Electrode One-Device Cell appearing in the IBM Technical Disclosure Bulletin, Vol. 15, No. 6, November 1972, pages 1765 and 1766, a single-device cell is described of the single field-effect transistor (FET) type, in the class of cells described in U. S. Patent No. 3,387,286. In the above-published article, the gate electrode and capacitor ground plate electrode are combined into a single electrode to provide a memory array cell with fewer metal connections and a higher packing density. In the cell shown, the N substrate is biased to ground.

It has been found that instead of a ground bias, the substrate should be biased so that the PN junction in the storage area is reversed biased in accordance with the following formula:

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