Browse Prior Art Database

Reducing Hot Carrier Injection into Gate Insulators

IP.com Disclosure Number: IPCOM000084474D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Gdula, RA: AUTHOR

Abstract

As shown, when field-effect transistor (FET) devices are made smaller, which improves the FET device density, the channel lengths 4 also get shorter. When a greater than 3.1 volt source-to-drain bias is applied across 4, hot carriers 8 are created beneath gate insulator 10, some of which are injected into and trapped in the gate insulator 10 creating high-charge levels near silicon surface 11.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 87% of the total text.

Page 1 of 2

Reducing Hot Carrier Injection into Gate Insulators

As shown, when field-effect transistor (FET) devices are made smaller, which improves the FET device density, the channel lengths 4 also get shorter. When a greater than 3.1 volt source-to-drain bias is applied across 4, hot carriers 8 are created beneath gate insulator 10, some of which are injected into and trapped in the gate insulator 10 creating high-charge levels near silicon surface
11.

The effect of the high-charge levels is to shift the FET device threshold, which makes it difficult or impossible for the FET device to operate correctly. Hot carrier injection into gate insulators is a universal problem for small geometry FET's, since most hot carriers are trapped within approximately 100 angstroms of the silicon surface.

This problem can be alleviated or solved by utilizing two experimental facts:

1. Boron 14 introduced substitutionally for Si in the SiO(2) structure near to or in the interface, greatly reduces trapping of injected electrons.

2. Boron has a greater affinity for SiO(2) than silicon (boron depletion).

Therefore, silicon substrates with an excess of boron impurity dopant are used to begin the fabrication of the desired FET devices. All processing up to and through the growth of the gate oxide insulator 10 is conventionally accomplished.

After the gate insulator 10 is formed, the excess boron in the silicon substrate is caused to migrate into the SiO(2) near the Si-SiO(2) interface by the ph...