Browse Prior Art Database

Data Buss Precharge

IP.com Disclosure Number: IPCOM000084479D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Hsieh, JC: AUTHOR

Abstract

This is a controller/engine that is organized around, and includes, a number of functional components, such as a register stack, stack control, and storage interface subsystem.

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Data Buss Precharge

This is a controller/engine that is organized around, and includes, a number of functional components, such as a register stack, stack control, and storage interface subsystem.

An 18-bit data buss, that is composed of a parallel set of 18 bi-directional lines, interconnects these components. Using the predrive capability of known drivers, a data buss precharge circuit 10, including a series connection of receiver R, inverter I, and AND circuit A, overcomes a critical delay data path problem. In addition, an available signal source is used to precharge the buss, rather than using a separate, independent, signal. The precharge circuit improves the performance of the data buss and eliminates bad data at input 3 of a latch on a receiving chip.

The precharge logic circuits 10 will not inhibit normal operation of a data buss. During the time when a data buss is discharging to ground through a driver by the latched data 2, the output 5 of the precharge logic circuits 10 is at a downlevel so that data buss operation is properly gated by the latched data only. However, prior to the data buss being charged by the down going latch data 2, the precharge circuit 10 helps to activate the predriver, which also charges up the buss.

In the event that the latched data 2 stays at an uplevel for the entire second machine cycle, the buss will have an up-down transition and eventually stays down when the clock input 4 at the latch on the receiving chip is up. In ne...