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Summing Circuit for Analog Levels

IP.com Disclosure Number: IPCOM000084489D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Falcoz, A: AUTHOR [+2]

Abstract

Shown in the drawing is a circuit to permit a weighted summation of analog levels to be performed.

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Summing Circuit for Analog Levels

Shown in the drawing is a circuit to permit a weighted summation of analog levels to be performed.

The circuit comprises a first set of field-effect transistors T1, 1 to T1.n and a second set of field-effect transistors T2.1 to T2.n, each transistor having three electrodes namely source electrode s, drain electrode d and gate electrode g, as shown for transistor T2.1.

Capacitors C1 to Cn are connected between drain d and gate g of transistors T2.1 to T2.n Capacitor CO is connected across transistor T1.n. Gates of transistors T1.1 to Tq.n are controlled through clock pulses 01, and gates of transistors T2.1 to T2.n are controlled through clock pulses 02.

Analog voltages V1 to Vn to be summed are applied to inputs 1 to n to input capacitors Ce-1 to Ce-n.

During the UP level of pulse train 02, output transistor TO and transistors T2.1 to T2.n are conductive. Consequently, capacitor CO is charged to: Co. Vref Vref being equal to the clock amplitude minus one threshold Bgs.

Capacitors C1, C2... and Cn are charged to C1.V1, C2V2,
...CnVn. When 01 goes UP, transistors T1.1 to T1.n become conductive and the charge of capacitor CO is transferred to capacitors C1 to Cn. the amount of charge of capacitors C1 to Cn are C1 (Vref - V1), C2 (Vref-V2), Cn (Vref - Vn). Consequently after 01 the new charge of capacitor CO is: CO. Vref - C1 (Vref-V2) ...-Cn (Vref - Vn) which

Vref [CO -(C1 + C2 +... + Cn)] + C1V1 + C2V2 +... + CnVn.

By making CO = C...