Browse Prior Art Database

Producing Si Wafers Insensitive to Slip Lines

IP.com Disclosure Number: IPCOM000084495D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Bohg, A: AUTHOR [+2]

Abstract

Wafers are produced by slicing Si-rods. The saw blade used for this purpose is not guided sufficiently accurately to ensure that completely plane parallel wafers are obtained. As a result of the existing protrusions or indentations, the sawed wafers yield to the pressure of the lapping disks during the subsequent bilateral lapping process.

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Producing Si Wafers Insensitive to Slip Lines

Wafers are produced by slicing Si-rods. The saw blade used for this purpose is not guided sufficiently accurately to ensure that completely plane parallel wafers are obtained. As a result of the existing protrusions or indentations, the sawed wafers yield to the pressure of the lapping disks during the subsequent bilateral lapping process.

The wafers thus produced form slip lines during the later heat cycles, thus leading to dislocations and pipes during the semiconductor processes. This decreases the yield of the integrated circuits.

To reduce the influence of the slip lines, the saw blade is guided so that during slicing the sawed faces 2 are alternately concave and convex. In the drawing these faces 2 are shown on a rod 1.

The wafers obtained are alternately of a biconvex shape 3 and a bi-concave shape 4. During the subsequent plane parallel lapping process, the biconvex wafers 3 support themselves only on their centers and the biconcave wafers 4 on their periphery, so that they do not yield to and escape the pressure of the lapping disks. Consequently, the wafers retain a symmetrical shape. After heat treatment, the wafers thus produced show fewer slip lines than wafers produced by orthodox processes.

During slicing, the thickness (a) of the concave wafers in the center and the thickness (b) of the convex wafers 3 along the periphery must be at least equal to the thickness of the plane parallel wafers required.

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