Browse Prior Art Database

Reducing Hidden Stresses in Si Wafers

IP.com Disclosure Number: IPCOM000084496D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Bohg, A: AUTHOR

Abstract

Silicon wafers used as substrates for integrated circuits show hidden stresses. As a result of this, the wafers are severely deformed during high-temperature processes, such as epitaxial processes, and are interspersed from the periphery with a great number of dislocations. "Fresh" dislocations of this kind are undesirable, since they drastically reduce the yield of the devices which they are crossing.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

Reducing Hidden Stresses in Si Wafers

Silicon wafers used as substrates for integrated circuits show hidden stresses. As a result of this, the wafers are severely deformed during high- temperature processes, such as epitaxial processes, and are interspersed from the periphery with a great number of dislocations. "Fresh" dislocations of this kind are undesirable, since they drastically reduce the yield of the devices which they are crossing.

After sawing and prior to lapping, the wafers are subjected to a separate temperature process which produces a sufficiently great temperature difference between the center and the periphery of the wafer. This compensates hidden stresses and anticipates deformations that may occur during the subsequent critical semiconductor processes.

Surface irregularities which inevitably occur are eliminated by surface treatments, such as lapping and polishing. In comparison with "fresh" dislocations, the dislocations induced during the separate process are ineffective in the subsequent critical processes.

1