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High Speed Voltage Current Pulser

IP.com Disclosure Number: IPCOM000084507D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 81K

Publishing Venue

IBM

Related People

Prilik, RJ: AUTHOR

Abstract

A high-speed voltage/current pulser is described which selectively applies a programmable voltage pulse or a programmable current pulse to a device under test.

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High Speed Voltage Current Pulser

A high-speed voltage/current pulser is described which selectively applies a programmable voltage pulse or a programmable current pulse to a device under test.

Fig. 1 shows a block diagram, whereas Fig. 2 is a circuit schematic. The circuit can deliver either a current pulse or a voltage pulse at output G by selectively setting the relay K1. In the current mode, programmed current values E are preselected via a ladder network M to summing point F. This is accomplished via saturated transistor switches Q4 through Q11 and resistors R17 through R32.

When logic input A in the gated regulator L goes more negative than C, transistor Q1 turns 'off' and transistor Q2 turns 'on'. Point D goes from a +V(cc) value to a reference voltage established by B thru an emitter-follower transistor Q3. The reference voltage at D (established by zener diode D1) turns on the output transistor drivers Q12, Q13, and Q14 in parallel. Summing point F assumes a voltage value equal to B (V(be) of Q3 is cancelled by V(be) of Q12, Q13 and Q14). I(out) is defined as the reference voltage B divided by the total programmed ladder network resistance.

When logic input A goes more positive than C, Q1 turns on and Q2 turns off, point D returns to +V(cc) via R40. Output drivers Q12, Q13 and Q14 turn off. I(out) assumes a zero value. +V(cc) power supply variations have little effect on I(out), due to the floating reference B via diode D1.

Point D reference voltage (Delta V) remains constant, due to current sharing of Q2 collector current via Q3 and the output drivers Q12, Q13 and Q14.

V(be) variations in Q12, Q13 and Q14 under different program currents have minimal effect, due to a nominal reference voltage being orders of magnitude higher than V(be) variations. Thermal balance of Q12, Q13 and Q14 is accomplished via R33, R34, R35 emitter resistors and a common transistor heat sink.

Power dissipation and Beta effects of transistors Q12, Q13 and Q14 are minimal due to parallel operation.

The output of the current pulser K is routed via K1 to output G, having a magnitude which is digitally programmed via the current ladder M and having a pulse width equal to the width of the input logic gate A. Typical applications of this circuit provide a zero to greater than 100MA current pulse, with a greater than 15V compliance voltage-and an accuracy of + or - 1%.

In the voltage mode, the mode select relay K1 routes the current pulser output into a termination resistor R45 via the normally closed contacts of relay K1. The voltage generated at H is buffered via the voltage transistor drivers Q15, Q17, Q18...