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Active Circuit for Neutralizing Capacitive Loading

IP.com Disclosure Number: IPCOM000084508D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

McKinnon, JD: AUTHOR

Abstract

A circuit is described for neutralizing the capacitive loading on a semi-conductor device under test having a high-output impedance.

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Active Circuit for Neutralizing Capacitive Loading

A circuit is described for neutralizing the capacitive loading on a semi- conductor device under test having a high-output impedance.

The semiconductor device under test (D.U.T.) 2 is comprised, for example, of field-effect transistor (FET) integrated circuits which have a relatively high-output impedance on the order of 1200 ohms. To maintain the fast rise time of approximately 50 nanoseconds for the signal output from the device under test 2, it is essential to avoid loading the output of the device with a capacitance greater than 50 picofarads. However, in typical semiconductor device testing arrangements, the distance separating the device under test 2 from the tester 6 is on the order of 2 feet. Coaxial cable 4 connecting the device under test 2 to the tester 6 will have a capacitance of at least 125 picofarads, well exceeding the desired limit for the capacitive loading of the device under test 2.

The circuit described compensates for the excessive output capacitance 5 of the coaxial cable 4, by supplying a compensating electric charge at the node 8, to assist in the process of charging the capacitance 5 of the coaxial 4.

The circuit consists of a DC operational amplifier 10 having a high-gain, low- input impedance, and a capacity to supply up to 100 milliamperes of current at its output 12. The negative terminal of the amplifier 10 is connected through a first resistor 11 to ground and through a second res...