Browse Prior Art Database

Accumulative Distribution Decoder

IP.com Disclosure Number: IPCOM000084513D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Dias, WC: AUTHOR [+3]

Abstract

Described is a hardware monitor devoted to the capturing, decoding, and recording of event occurrence on an 8-bit computer type bus. Its data flow is illustrated in the attached figure.

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Accumulative Distribution Decoder

Described is a hardware monitor devoted to the capturing, decoding, and recording of event occurrence on an 8-bit computer type bus. Its data flow is illustrated in the attached figure.

Input connections for the bus points, strobe(s), and control signals are made with measurement probes having the capability of-spanning various voltage levels, and presenting a "no load" condition on the host line.

The bus lines are controlled through variable-logic functions in the control logic block and, if acceptable, sent to one of the two input buffers A or B. The input buffers are 8-position shift registers controlled by the "tracking bit" method of identifying active data, and are used to smooth out peak input activity. When a buffer is full, it switches input acceptance to the other buffer, and empties it's contents to the address register/counter at a predetermined rate.

The data now in the address register becomes a storage address, and a storage cycle is generated. This fetches the storage work (24 bits) which is now incremented by 1, and stores the new count back into the same location, and enables the address register to accept the next address from the buffer.

When the storage counter becomes full (16,777,216), it gates the decoded storage address bus to the output buffer for a printer indication of the overflow count, while the storage counter is stepped to zero and awaits its next increment. Data is not held in the output buffers...