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Dynamic Threshold Setting Circuit

IP.com Disclosure Number: IPCOM000084519D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 4 page(s) / 95K

Publishing Venue

IBM

Related People

Penny, RE: AUTHOR

Abstract

Described is a dynamic threshold setting which rejects noise and increases the accuracy of mark edge location. Fig. 1 shows a basic prior art circuit suitable for use in a scanner. The input is a voltage signal proportional at each instant to the light reflected from a document being scanned by a thin light beam. The output is a digital signal which should ideally indicate at each instant the presence or absence of a printed mark. Thus, transitions at the output should occur precisely at the edges of the printed marks.

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Dynamic Threshold Setting Circuit

Described is a dynamic threshold setting which rejects noise and increases the accuracy of mark edge location. Fig. 1 shows a basic prior art circuit suitable for use in a scanner. The input is a voltage signal proportional at each instant to the light reflected from a document being scanned by a thin light beam. The output is a digital signal which should ideally indicate at each instant the presence or absence of a printed mark. Thus, transitions at the output should occur precisely at the edges of the printed marks.

Fig. 2 shows the waveforms of this circuit. The object of the circuit is to select as the threshold for each transition, the voltage halfway between the extremes of the input signal on each side of that transition. This requires that the extreme attained immediately following the transition be "known" in advance to establish the threshold. This is accomplished by using a delay line having a time delay longer than the rise time (and fall time) of the signal. Positive and negative peaks are set up by the undelayed signal, and a voltage divider between them gives the threshold, which is compared to the delayed signal. The peak detectors are allowed to leak so that a "setup" can be made on each new peak.

The basic limitations of this circuit are:
1. By the time the delayed signal makes a transition, at

least one of the stored peaks has leaked, causing some

inaccuracy in the threshold.
2. If a wide interval is crossed, one of the peak stores

will leak until it hits the signal at which time slight

noise fluctuations will switch the output. This is

shown on the last part of the timing diagram in Fig. 2.
3. If the leak rate is made slow in order to alleviate

No. 2, then a peak less extreme than the previous

peak of like polarity may not set up the peak store.

This is shown on the first positive leak in Fig. 2.

Fig. 3 shows an improved circuit which removes these limitations. The peak store circuits are designed to hold until given a digital leak signal, at which time they leak at a constant volts per second rate. They also provide a digital output indicating whether the store is charging or not.

The basic design of the positive peak stores is shown in Fig. 4. Operational amplifier A1 is used for low-offset voltage on the stored peak. Amplifier A2 is a voltage follower for isolating the storage capacitor C from the output load. The comparator gives a "1" output if the capacitor is charging and a "0" output if it is holding or leaking. The leak input activates the constant-current source which causes the stored value to leak. The negative peak store is identical except that diodes D1 and D2, Compare, and the current source have opposite polarity.

Fig. 5 shows the waveforms of the improved circuit. The positive and negative leak signals are controlled by flip-flops FF2 and FF3, respectively, which starts the leaking only after a stored peak has been used and is no longer needed....