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Multiprogramming Process Controller

IP.com Disclosure Number: IPCOM000084534D
Original Publication Date: 1975-Nov-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 15K

Publishing Venue

IBM

Related People

Gladney, HM: AUTHOR [+3]

Abstract

A set of techniques is described to allow a single minicomputer to accomplish multiprogramming of various applications at appropriate priorities. They make possible independent preparation of separate application programs. This is permitted by considering the applications as each comprising separate sections of code, so that the vast majority of each application will be served at a low priority, and the response-sensitive or synchronization portions of the programs can preempt service with high-priority levels.

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Multiprogramming Process Controller

A set of techniques is described to allow a single minicomputer to accomplish multiprogramming of various applications at appropriate priorities. They make possible independent preparation of separate application programs. This is permitted by considering the applications as each comprising separate sections of code, so that the vast majority of each application will be served at a low priority, and the response-sensitive or synchronization portions of the programs can preempt service with high-priority levels.

The specific set of techniques or mechanisms with exemplary machine cycle constraints is described as follows:

1) A single processor with three or more hardware priority interrupt levels and a full set of registers for each level; the processor shall have the ability to switch from a lower level to a higher level on receipt of the external (or internal) signal, and to detect which of several interrupt signals occurred. The processor should include a clock precise to the highest precision with which external events are to be recorded. Alternatively, an appropriate precise digital clock which can be read by the processor must be provided externally.

2) If the processor includes time-sensitive devices internally, such as disks or telecommunication lines, these are to be assigned to the second highest interrupt level so that they cannot interfere with servicing the highest level. Overruns or delays on these devices are to be handled with normal error mechanisms.

3) The majority of each application program is to be executed on the lowest processor level. The system must provide a mechanism by which control will be regained by a supervisory program at least every 200 memory cycles; there are several ways of providing this. One example which is used in the feasibility demonstration is an emulator for realtime commands in which each command is executed by an emulator subroutine, which either requires less than 200 memory cycles or which returns control to the supervisor every 200 memory cycles.

Alternatively, an application program may be translated by a compiler which inserts a return to supervisor control at appropriate points in the machine instruction sequence. Alternatively, the lowest hardware priority level can be replaced by as many hardware priority levels as may be desired for preemption levels. The supervisor must have task switching ability; whenever it regains control, it should switch service to the highest priority task then ready.

4) Those program segments which do not have important timing requirements are to be run as the lowest priority tasks served by mechanism

(3). References 1-3 describe examples of tasks which need no timing guarantees. This type of task is the most common in sensor-based applications.

5) Those program segments in which response time precision requirements are of the order of 200,000 memory cycles or slower, to be ru...