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Parity Tree Error Checking

IP.com Disclosure Number: IPCOM000084559D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Curlander, PJ: AUTHOR

Abstract

A parity checking tree for a data bus has its operation validated by alternating parity input with clock times and detecting an exclusive OR (OE) output.

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Parity Tree Error Checking

A parity checking tree for a data bus has its operation validated by alternating parity input with clock times and detecting an exclusive OR (OE) output.

Output from the OE tree is sampled in phase-hold circuit PH at time A. Input to the OE tree is at time B, which is the alternate phase of a control clock. By imposing an OE circuit intermediate to bus parity bit P and the OE tree, alternate good and bad parity is forced through the OE tree. Correction is made at the output through an OE circuit. The OE tree decision is predicted by the MOD 2 toggle latch actuated by the B clock pulse.

In a first cycle, input OE is actuated for inverting parity into the input OE tree. Simultaneously, output OE has the opposite or true indication for passing true parity, as well as verifying that the parity in PH is true. In the next phase, the MOD 2 toggle latch has its state reversed such that the parity signal on line P is inputted to the OE tree as true parity. Simultaneously, output OE has its output inverted for indicating inverse parity.

The above principles can be applied to any logic system of the error checking, error transferring, error translation type.

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