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Logic Array Checking

IP.com Disclosure Number: IPCOM000084560D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Curlander, PJ: AUTHOR

Abstract

Using programmable logic arrays creates a need for error detection capability in such arrays. Such error detection is particularly useful when the programmable logic arrays (PLA's) control other apparatus. Because of the inherent high reliability, single error detection in the search and read array of a PLA appears satisfactory.

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Logic Array Checking

Using programmable logic arrays creates a need for error detection capability in such arrays. Such error detection is particularly useful when the programmable logic arrays (PLA's) control other apparatus. Because of the inherent high reliability, single error detection in the search and read array of a PLA appears satisfactory.

One design constraint required for achieving such error detection is that the set of all word lines be mutually exclusive and exhaustive; i.e., only one word line is active at a given sequential machine state, and one word line is always active in each sequential machine state. The usual array logic design procedure is a direct transformation from a machine state diagram to an array logic bit pattern.

Following the generation of a bit pattern, a next design step may include reduction of word lines by inspecting bit patterns and then combining words having identical bit patterns. But, machine state transitions will usually be unique allowing only a minimal reduction in the number of word lines. If this reduction is foregone, the design constraint can be achieved.

Word lines representing different machine states are mutually exclusive. Word lines representing the same state, but different portions of the state, are also mutually exclusive. Word lines which are not mutually exclusive are those representing the same machine state and the same portion of that state. Such occur when it is necessary to perform a logical OR function of several search or AND array variables. Such logic OR-related word lines can be made mutually exclusive by adding bits to the search array, such that each line becomes unique due to the added or redundant bits. The latter represents the final step of array logic design.

Next, the exterior circuitry to the PLA must be designed. Each word line has one of two output lines active according to the parity of the machine state represented by that word line. Exemplary bit patterns are set forth in the table below. AND ARRAY READ ARRAY.

Word Data Check Data

Line Inputs Inputs Outputs Y1 Y2 Y3 Y4 A B C1 C2 C3 P 1 XXXX 1 1 1 0 XXXX 0 1 0 0 0 0 2 XXXX 1 1 1 1 1 0 0 0 0 1 3 0XX1 1 0 0 0 0 1 1 0 0 0 4 1XX0 1 0 0 0 0 1 0 1 0 1 5 0XX0 1 0 0 0 .... 0 1 0 0 1 0 6 XXXX 1 0 1 1 0 1 0 0 0 0 7 XXXX 1 0 0 1 1 0 1 0 0 0 8 XXXX 1 0 0 1 1 0 0 1 0 1 9 XXXX 0 0 0 1 XXXX 0 1 0 0 0 0.

In the above table, X's in the data input and outputs indicate data patters. Check inputs, or state variables Y1-Y4, provide the extra checking in...