Browse Prior Art Database

Antiglitch Scheme for Signal Multiplexors

IP.com Disclosure Number: IPCOM000084607D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Miller, GA: AUTHOR [+2]

Abstract

Signals to the multiplex circuit are held quiescent when the clock pulse is applied to the data register. The clock allows new data to be inserted into the data register latches. Voltage transitions at the outputs of the data register are applied to the multiplex gates.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Antiglitch Scheme for Signal Multiplexors

Signals to the multiplex circuit are held quiescent when the clock pulse is applied to the data register. The clock allows new data to be inserted into the data register latches. Voltage transitions at the outputs of the data register are applied to the multiplex gates.

Undesirable signals or glitches can appear at the output A because of delay variability within the register latches and in the multiplex gate circuits. The antiglitch polarity hold latch is forced to be in its "hold mode" by the same clock signal that enables the data register. Time delays in the hold signal and within the polarity hold latch should be one order of magnitude shorter than delays through the register and multiplex path. The data register latches can be made purposely slow by designing them at low levels of power.

The undesirable signals or glitches are prevented from appearing at the output B, by latching-on to the multiplex circuit output level just before the multiplex gates go through their transitions.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]