Browse Prior Art Database

Single Programmable Read Only Memory as an Initial Microprogram Load

IP.com Disclosure Number: IPCOM000084608D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Phillips, BR: AUTHOR

Abstract

This method allows a small nonvolatile bit storage device, i.e., a single programmable read-only memory (P/ROM), to establish control for carrying out the initial microprogram load (IMPL) of a processor that uses a volatile control storage (CS).

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Single Programmable Read Only Memory as an Initial Microprogram Load

This method allows a small nonvolatile bit storage device, i.e., a single programmable read-only memory (P/ROM), to establish control for carrying out the initial microprogram load (IMPL) of a processor that uses a volatile control storage (CS).

The P/ROM is an electrically alterable read-only memory chip organized as 256 addresses with 4 bits at each address. The P/ROM is addressed by a register (PADR) and the contents of the addressed location are loaded into a parallel load/serial right-shift register (AREG).

The flow diagram of the control algorithm shown restructures 252 four-bit data words from the P/ROM into a bootstrap microprogram of 28 thirty-six bit microinstructions and loads them into CS. An address register (PC) identifies the location in CS where the microinstruction is loaded from data register (DREG). After all 28 microinstructions have been formed and loaded into CS, PC is set to 0 and the processor starts execution of the microprogram.

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