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Diagnosing Faults in Complex Logic Semiconductor Circuits

IP.com Disclosure Number: IPCOM000084621D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Morrissey, JM: AUTHOR [+3]

Abstract

In complex logic large-scale integrated circuits it is often difficult to locate the specific cause (mechanism) of a failing circuit. This is especially true when a circuit fails under AC conditions but functions at DC rates.

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Diagnosing Faults in Complex Logic Semiconductor Circuits

In complex logic large-scale integrated circuits it is often difficult to locate the specific cause (mechanism) of a failing circuit. This is especially true when a circuit fails under AC conditions but functions at DC rates.

Testing can usually locate a cell where the mechanism probably is but cannot localize it further. The figure is a block diagram of a portion of a logic circuit. Testing has localized a failure to cell BC; however, the outputs of the A cells or the inputs of the C cells could also be at fault.

Set conditions are introduced into the circuit in a sequence, or in a pattern if all chips have the same failure mode. To accomplish this, a laser is focused on device structures and shorts these or metal lands and opens other metal lands.

The chips are then tested and the response to the real fault and the set condition is analyzed. This operation may be performed a number of times if only one chip has the specific failure mechanism until it is localized.

This technique is particularly useful in cases where more than one mechanism is causing the failure mode. It may also be used to introduce failures in complex circuits to understand how types of failure mechanisms cause failure modes.

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